1. Field of the Invention
The present invention relates to a large scale integrated circuit (LSI) which includes gate array circuits comprising MIS (metal insulator semiconductor) or CMIS (complementary MIS) type FETs (field effect transistors), more particularly to its output buffer circuit. The present invention is intended to reduce a noise induced by variation of high current, or to stabilize a fluctuation of earth potential which are caused by switching of output buffer circuits.
2. Description of the Prior Art
General LSIs are provided with input buffer circuits (or level shifter) which equalize signal level of input signal to that of inner logic circuits, and output buffer circuits which drive outer circuits or equipments. Recently as the scale of integration in LSI becomes large, the gate number included in LSI is exceeding few tens of thousand gates per chip, and the output gate number also exceeded two hundreds. The output buffer circuit is required high switching speed and driving capacity in order to drive various kinds of external load. On the other hand there appeared another problem of noise, which is induced by high switching current of the output circuit. It is becoming a serious problem for LSI or VLSI (very large scale integration) circuits, of which main logic is designed to operate with very small current.
In order to render clearly apparent such situation and the advantage of the present invention, prior art output buffer circuit and its design concept will be described briefly. Circuit diagrams for some exemplary output gate circuits are shown in FIGS. 1 through 3. In which, FIG. 1 is a non-inverting output buffer circuit, FIG. 2 is an inverting output buffer circuit and FIG. 3 is a NAND type output buffer circuit exemplifying an output buffer circuit coupled with a NAND gate. Throughout the figure, (a) shows a symbol mark of the circuit and (b) shows inner connection of the gate circuit. In the figures IN designates input terminal which connects the gate circuit to the inner logic circuit, OUT is an output terminal, and G.sub.1 is a driver gate for the output buffer gate circuit G.sub.2. V.sub.DD is a high voltage source and V.sub.SS is a low voltage source (usually earth potential). As can be seen in the figures, the output buffer gate circuit G.sub.2 consists of a complementary MOS (CMOS) circuit comprising p-channel MOS (p-MOS) FET T.sub.1, and n-channel MOS (n-MOS) FET T.sub.2.
Driving force or driving capacity of the output buffer circuit is determined by output impedance or mutual conductance gm of the CMOS FETs T.sub.1 and T.sub.2. Following relation is known in the art EQU gm.varies..beta..varies.W/L
where .beta. is current amplification factor of the transistor, W is gate width of the FET and L is gate length of the FET. Therefore, high driving capacity of the output buffer circuit is attained by shortening the gate length L and making W large that is elongating the transistor.
In prior art LSI the the ratios W/L of transistors for inner gate G.sub.0, for driving gate G.sub.1 and for output buffer gate G.sub.2 are determined respectively as 1:3:10 or 1:5:20 for example, in the design stage of the LSI. These ratios were determined to minimize the chip area, or to minimize the switching time of the output buffer gates.
Recently there appeared some attempts to optimize the size of output buffer circuit and its driving stage. For example, Japanese Provisional Publication No. 57-148363 by K. Kinoshita (laid open on Sep. 9, 1982) or No. 58-127347 by S. Wakamatsu (laid open on Jul. 29, 1983) show some of them. They are attempting to optimize the output circuit introducing the idea of master slice technology, namely plurality of transistors (FET) having predetermined sizes (for example three kinds of sizes having the size ratio of 1:2:3) are fabricated at the I/O (input/output) circuit area of IC chip, and they are connected properly by wiring pattern.
FIG. 4 illustrates the outline of those attempts. In the figure, (a) shows a part of the I/O area which is generally located at the peripheral part of the chip. As shown in the figure, 11 are smallest size FETs, 12 are second size FETs whose size is twice of that of FETs 11, and 13 are largest FETs (tree times as large as Fets 11). And if two fun out circuit or three fun out circuit are required as shown in FIG. 4(b) or 4(c), proper size FETs are selected and connected each other as shown in the figure. For example, for a two fun out circuit the second size FET 15 is used to drive two small size FETs 14, and for a three fun our circuit the largest size FET 17 is used to drive three small FETs 14. In such a a manner, the decrease of switching speed is prevented.
As has been described before, prior art output gate circuits are designed to operate as fast as possible. The high speed and high driving capacity of the output buffer circuit is attained by increasing the switching current handled by output transistors. But high current switching has increased problem of induced noise, especially for very large scale integrated circuit (VLSI). The inner logic circuit, which is a main part of the logic circuit, is designed to work with a current as small as possible to prevent heat dissipation, but the output circuit cannot cut down the switching current to drive outer circuit which generally has large stray capacity. Moreover, as the number of output buffer circuit increases, there occurs a chance that several number of output circuits work at the same instant, so the multiplied switching current induces noise in the wiring lines or pins in the package, and causes malfunction of the main logic. This is becoming a serious problem for VLSI circuits.
The voltage fluctuation V.sub.N appears on the V.sub.SS line is given as EQU V.sub.N =RI+L[(dI)/(dt)]
where R is resistance of the wiring, L is inductance of the V.sub.SS line and I is the current flowing in the V.sub.SS line. This voltage fluctuation causes the noise and malfunction of the inner circuit. So, if the circuit is designed to have a large value of W/L in order to get high switching speed or high driving capacity, the current amplification factor .beta. becomes large. Since the current I is proportional to .beta., which is proportional to W/L.
There exists a trade off, therefore, between getting high speed switching or high driving capacity and decreasing switching noise. Especially it is serious for LSI or VLSI circuit, wherein many of the output buffer circuits have chance to work at the same time, and by the sum of the switching currents, noise is induced on the V.sub.SS line or on the V.sub.DD line which causes malfunction of the main logic circuit.